1. Field of the Invention
The present invention relates to a semiconductor device comprising an enhancement-mode (E-mode) field-effect transistor (FET) and a depletion-mode (D-mode) FET which are operated at a high speed by using a two dimensional electron gas (2 DEG), and to a method of producing the semiconductor device.
2. Description of the Related Art
Each of the above-mentioned FETs has a hetero-junction and is well-known as a high electron mobility transistor (HEMT).
In general, the above FET's comprise a semi-insulating gallium-arsenide (GaAs) substrate, an undoped GaAs channel layer, an n-type aluminum-gallium-arsenide (AlGaAs) electron-supply layer, and an n-type GaAs cap layer, which layers are successively formed on the substrate. A threshold voltage Vth of the FET depends on the thickness of a semiconductor layer including the n-type AlGaAs electron-supply layer between the undoped GaAs channel layer and a contacting bottom portion of a gate electrode. This thickness is controlled to a depth of a gate electrode recess formed in the semiconductor layers by an etching process.
Furthermore, integrated circuit devices composed of HEMTs, DCFL (direct coupled FET logic) circuits are widely used as basic inverter circuits. The inverter circuit has an enhancement/depletion (E/D) constitution comprising an E-mode HEMT at a drive side and a D-mode HEMT at a load side. In an E/D constitution semiconductor device for the inverter circuit, it is necessary to form the E-mode HEMT having one threshold voltage and the D-mode HEMT having another threshold voltage in the same semiconductor substrate. PG,3
Current demands for an increase in the speed of computer systems have led to the development of compound semiconductor integrated circuit devices having a very high-speed operation.
In order to meet the above demand, it is necessary not only to improve the high-speed operation but also to increase the reliability of these devices, and therefore in the HEMTs constituting the integrated circuit device, the gate length of the HEMT is shortened to enable improve a higher speed operation. Further, it is necessary to provide the following properties:
(a) low source resistance Rs; PA1 (b) small parasitic capacitance Cp; and PA1 (c) excellent gate properties including a high gate breakdown voltage.
Furthermore, it is necessary to easily and simultaneously form the E-mode and D-mode HEMTs having the above properties on the same semiconductor substrate.
A method of producing the E/D constitution semiconductor device in which the E-mode and D-mode HEMTs are simultaneously formed on the same substrate has been proposed, for example, in U.S. Pat. No. 4,615,102. According to this U.S. Patent, the semiconductor device is produced in the following manner (refer to FIGS. 1 to 8).
As illustrated in FIG. 1, on a semi-insulating GaAs substrate 1, an undoped GaAs channel layer (a first semiconductor layer) 2, an n-type AlGaAs electron-supply layer (a second semiconductor layer having an electron affinity smaller than that of the GaAs layer 2) 3, an n-type GaAs threshold voltage adjusting layer for the D-mode HEMT (a third semiconductor layer) 4, an n-type AlGaAs first stoppable layer (a fourth semiconductor layer) 5, an n-type GaAs ohmic-contactable layer (a fifth semiconductor layer) 6, an n-type AlGaAs second etching-stoppable layer (a sixth semiconductor layer) 7, and an n-type GaAs ohmic-contactable layer (a seventh semiconductor layer) 8 are formed (i.e., epitaxially grown) in sequence by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method.
As illustrated in FIG. 2, to isolate the E-mode HEMT and the D-mode HEMT from each other, the semiconductor layers 8 to 2 and the semiconductor substrate 1 are selectively etched by a wet etching method using a suitable etchant, e.g., hydrofluoric acid (HF), to form a groove 9, an E-mode transistor region "E" island, and a D-mode transistor region "D" island. This groove 9 extends into the substrate 1. In place of the etching treatment an ion-implantation treatment can be adopted, and in this case, oxygen ions or protons are doped into the portion corresponding to the groove 9 to form an insulating region.
As illustrated in FIG. 3, portions of the n-type GaAs layer 8 and the n-type AlGaAs layer 7 corresponding to a gate region of the E-mode transistor are selectively etched by a suitable etching method (e.g., a wet etching method using HF solution to form a recess 10 in the E region. A portion of the n-type GaAs layer 6 is exposed in the recess 10 and may be simultaneously etched.
As illustrated in FIG. 4, an insulating layer 11 being of, e.g., silicon dioxide (SiO.sub.2), is formed over the whole of the exposed surface by a chemical vapor deposition (CVD) method. The insulating (SiO.sub.2), layer 11 is coated with a resist layer (not shown) having openings and is then selectively etched by e.g., a wet etching method using an HF solution, to form contact openings therein. Leaving the resist layer, a metal film of AuGe/Au, AuGe/Ni/Au, AuGe/Ni, or the like is formed on the resist layer and the exposed portions of the seventh n-type GaAs layer 8 in the openings by a vapor deposition method. The resist layer is then removed by a suitable solvent, whereby a portion of the metal film on the resist layer is also removed. As the result of such a lift-off process, electrode metal portions 12, 13, 14, and 15 remain on the seventh n-type GaAs layer 8, and a heat treatment for alloying is carried out to form ohmic-contactable electrodes 12 to 15 of the source and drain electrodes of the E-mode and D-mode HEMTs.
As illustrated in FIG. 5, a resist layer (a masking layer) 16 is coated, exposed, and developed to form openings 17E and 17D for the formation of grooves for gate electrodes of the E-mode and D-mode transistors, respectively. By using the resist layer 16 as a mask, the SiO.sub.2 layer 11 is etched through the openings 17E and 17D by, e.g., a wet etching method using an HF solution, so that openings 18E and 18D are formed in the SiO.sub.2 layer 11. Then a selective dry etching treatment, in this case a reactive ion etching (RIE) treatment using an etchant gas comprising CCl.sub.2 F.sub.2, is performed to anisotropically etch the fifth n-type GaAs layer 6 in the E region through the opening 17E and the seventh n-type GaAs layer 8 in the D region, to form openings 19E and 19D, respectively. The fourth n-type AlGaAs layer 5 in the E region and the sixth n-type AlGaAs layer 7 in the D region serve as etching-stoppable layers.
The above-mentioned RIE method using CCl.sub.2 F.sub.2 gas can etch GaAs about 200 times faster than AlGaAs. The etching is automatically stopped at the surfaces of the n-type AlGaAs layer 5 and 7.
As illustrated in FIG. 6, the exposed portions of the AlGaAs layers 5 and 7 in the openings 17E to 19E and 17D to 19D are etched by, e.g., a wet etching method using an HF solution, to expose the third n-type GaAs layer 4 in the E region and the fifth n-type GaAs layer 6 in the D region. Since this etching treatment is performed for the purpose of removing a AlGaAs layer, and since the thickness of the AlGaAs layers 5 and 7 is thin, it is easy to control the etching of the AlGaAs layers 5 and 7 without the complete removal of the third and fifth GaAs layers 4 and 6. As the result of the etching, openings 20E and 20D are formed in the AlGaAs layers 5 and 7 and portions of the GaAs layer 4 and 6. It is possible to perform the etching treatment by a dry etching method.
As illustrated in FIG. 7, a selective dry etching (in this case, RIE) treatment using CCl.sub.2 F.sub.2 gas is performed so as to etch the third GaAs layer 4 in the E region through the opening 17E and the fifth GaAs layer 6 in the D region through the opening 17D so that openings 21E and 21D are formed, respectively. The second n-type AlGaAs layer 3 in the E region and the fourth n-type AlGaAs layer 5 in the D region serve as etching-stoppable layers. As the result of the above-mentioned etching treatments, grooves 22E and 22D consisting of the openings 18E to 21E and 18D to 21D, respectively, are completed.
As illustrated in FIG. 8, a metal layer for a Schottky barrier of, e.g., aluminum (Al), is formed by, e.g., a vapor deposition method, on the remaining resist layer 16 and in the grooves 22E and 22D. The resist layer 16 is then removed by a suitable solvent, whereby a portion of the metal film on the resist layer 16 is also removed. As the result, metal portions, i.e., gate electrodes 23 and 24 of the E-mode and D-mode HEMTs, respectively are formed. Therefore, a semiconductor device comprising the E-mode and D-mode HEMTs is obtained.
According to the above-mentioned production method of the prior art, the etching treatments and the gate electrode formation through the openings 18E and 18D of the insulating layer 11 are performed in a self-alignment system, and it is possible to easily produce a semiconductor device comprising the E-mode and D-mode HEMTs and having accurately controlled threshold voltages Vth.
To increase the operation speed of a DCFL circuit composed of the E-mode and D-mode HEMTs shown in FIG. 8, it is necessary to enable the drive-side transistor, i.e., the E-mode HEMT, to operate at a higher speed. As an expedient to this end, the gate length of the E-mode HEMT is shortened to 1 .mu.m or less, i.e., on the order of submicrons. But, in this case, a lowering of the source resistance Rs and the parasitic capacitance Cp become serious problems.
In the semiconductor device shown in FIG. 8, the regulation of the thickness of the n-type GaAs ohmic-contact layer 6 may be used to solve these problems. Since the n-type GaAs layer 4 serves to adjust the threshold voltage Vth, the thickness thereof is determined in accordance with the circuit performance conditions of the integrated circuit semiconductor device, and can not be easily changed. Furthermore, the n-type AlGaAs etching stoppable layers 5 and 7 are substantially formed in a thin state, and thus these layers can not be included in the parameters for solving the problems.
To lower the source resistance Rs of the E-mode transistor, the thickness of the n-type GaAs layer 6 can be increased, but as apparent from FIG. 8, the increased layer thickness involves an increase of the contact area between the layer 6 and the gate electrodes 23 and 24, with the result that the parasitic capacitance Cp is increased and a leakage current between the electrodes 23 and 24 and the layer 6 is also increased, whereby the gate breakdown voltage of the E-mode and D-mode transistors is lowered. On the other hand, to increase the gate breakdown voltage and to lower the parasitic capacitance Cp of the transistors, preferably the n-type GaAs layer 6 is made thinner. The thinned layer 6, however, brings an increase of the source resistance Rs and a lowering of the trans-conductance gm of the transistors.
An improved gate structure for the E/D constitution semiconductor device has been proposed, by which the above-mentioned antinomy is eliminated. This improved gate structure is formed in the following manner, referring to FIG. 9 and 10 in which the reference numerals and symbols used in FIG. 1 to 8 represent the same portions or corresponding portions of the device of FIGS. 1 to 8.
FIG. 9 shows a production stage corresponding to that shown in FIG. 5 of the prior art. In this case, the simultaneous etching step of the n-GaAs layer 6 in the E-mode portion and the n-GaAs layer 8 in the D-mode portion is carried out in an isotropic manner, instead of the anisotropic manner used in FIG. 5. Accordingly, the formed openings 19E and 19D extend in a transverse direction. The isotropic etching can be performed by controlling a gas pressure and a bias voltage in an RIE method using CCl.sub.2 F.sub.2 etching gas, which maintains the high selectivity of GaAs to AlGaAs.
FIG. 10 shows a production stage corresponding to that shown in FIG. 8. The production steps up to this stage are the same as those carried out in FIGS. 6 to 8.
In the produced semiconductor device having the improved gate structure, the gate electrodes 23 and 24 do not come into contact with the n-type GaAs layers 6 and 8, respectively, as shown in FIG. 10. Therefore, the obtained semiconductor device exhibits a lower parasitic capacitance Cp and a smaller amount of leakage current to thereby improve the gate breakdown voltage, compared with the semiconductor device explained in connection with FIG. 1 to 8. Furthermore, since the gate electrode 23 of the E-mode region does not come into contact with the n-type GaAs layer 6, an increase of the thickness of the layer 6 for reducing the source resistance Rs does not cause an increase of the parasitic capacitance of the E-mode transistor.
Nevertheless, the increase of the thickness of the n-type GaAs layer 6 still causes an increase of the contact area between the gate electrode 24 and the layer 6 in the D-mode region, which increases the gate leakage current and reduces the gate breakdown voltage of the D-mode transistor, as mentioned above. Therefore, the deterioration of the gate properties of the D-mode transistor prevents the formation of Schottky diodes between the gate electrode 24 and the source and drain electrodes 14 and 15, hinders the designing of an integrated circuit, and lowers the reliability of the semiconductor device.
To solve the above-mentioned problem in the D-mode transistor, a simultaneous etching of the n-type GaAs layer 4 in the E-mode region and the n-type GaAs layer 6 in the D-mode region has been considered for forming the openings 21E and 21D shown in FIG. 7 in the isotropic manner instead of the anisotropic manner, so that the openings 21E and 21D extend in a transverse direction, as shown in FIG. 11. In this case, the gate electrode 24 is formed to not come into contact with the n-type GaAs layer 6, but a surface depletion layer of the E-mode transistor reaches the undoped GaAs channel layer 2 to hinder the operation of the E-mode transistor. Therefore, the last etching step for a formation of recesses (grooves) for the gate electrodes should be carried out anisotropically to bring a portion of the electrode 23 into contact with the layer 4.
In the above-mentioned explanation the E-mode and D-mode transistors are HEMTs utilizing a two-dimensional electron gas, but it is possible to use transistors utilizing a two-dimensional hole gas instead of the electron gas. A "two-dimensional carrier gas" includes the two dimensional electron gas and two-dimensional hole gas.